As electronic and computing devices evolve to provide more functionality and process more content, such devices demand larger storage capacities while, at the same time, increased power efficiency. Given their storage and bandwidth capacities, many electronic and computing devices employ dynamic random access memories (DRAMs) as the working memory of these devices.
Although there are multiple types and variations of DRAMs, most DRAMs require regular or periodic refreshing of the voltage levels in the cells of the DRAMS to retain the corresponding logic data stored therein. This is due to certain parasitic effects and leakage currents in the memory cells of the DRAMs which may, over time, degrade the stored voltage levels. Refresh operations occur during standby periods in which read/write operations to/from the DRAMs are idle. DRAMs typically have a self-refresh mode which, in concert with the standby period, involves turning off internal clocks and input channels while providing a clock enable (CKE) signal, issued by the memory controller, to trigger the self-refresh mode.
However, the increased functionality of electronic and computing devices, as noted above, presents certain challenges in reducing the power consumption of such memory devices.